Low-Power VLSI Techniques for Always-On Sensing

Abstract

Always-on sensing systems—such as environmental monitors, wearable devices, and IoT sensors— demand ultra-low power consumption to operate continuously with limited energy budgets. In VLSI implementations, reducing both dynamic and leakage power is essential to sustain prolonged operation without frequent recharging. This paper examines key low-power VLSI techniques tailored for always-on sensing applications. We explore circuit- and architecture-level strategies including clock gating, power gating, multi-threshold CMOS (MTCMOS), dynamic voltage/frequency scaling (DVFS), adaptive body biasing (ABB), sub-/near-threshold operation, and logic-level optimizations such as adiabatic logic and state encoding. Through a combination of theoretical analysis and synthesis experiments, we demonstrate that selective clock gating and power gating applied to idle sensing modules can cut dynamic and static power by up to 60–80%. Incorporating MTCMOS and ABB further reduces leakage during standby, enabling energy savings without significant performance degradation. Our methodology includes implementing a lowpower always-on sensor front end in a synthesized VLSI testbench, comparing baseline designs to each low-power enhancement. Results confirm that integrating power-aware techniques dramatically extends battery lifetime. We conclude with practical design recommendations for embedding power-reduction strategies in always-on VLSI systems and outline future directions such as wake-up receiver integration and sub-threshold analog front ends.